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Chapter 1: About DSP Builder
General Description
Provides a variety of fixed-point arithmetic and logical operators for use with the
Simulink software.
Enables rapid prototyping using Altera DSP development boards.
Supports the SignalTap ? II logic analyzer—an embedded signal analyzer that
probes signals from the Altera device on the DSP board and imports the data into
the MATLAB workspace to ease visual analysis.
Allows HDL import of VHDL or Verilog HDL design entities and HDL defined in
a Quartus II project file.
Supports hardware-in-the loop (HIL) to enable FPGA hardware accelerated
cosimulation with Simulink.
Supports Avalon ? Memory-Mapped (Avalon-MM) interfaces including user
configurable blocks, which you can use to build custom logic that works with the
Nios ? II processor and other Qsys designs.
Supports Avalon Streaming (Avalon-ST) interfaces including an Packet Format
Converter block and configurable Avalon-ST sink and Avalon-ST source blocks.
Allows you to instance Altera DSP MegaCore ? functions in a DSP Builder design
model.
Supports tabular and graphical state machine editing.
f For information about new features and errata in this release, refer to the DSP Builder
Release Notes and Errata .
General Description
Digital signal processing (DSP) system design in Altera programmable logic devices
(PLDs) requires both high-level algorithm and hardware description language (HDL)
development tools.
The Altera DSP Builder integrates these tools by combining the algorithm
development, simulation, and verification capabilities of The MathWorks MATLAB
and Simulink system-level design tools with VHDL and Verilog HDL design flows,
including the Altera Quartus II software.
DSP Builder shortens DSP design cycles by helping you create the hardware
representation of a DSP design in an algorithm-friendly development environment.
You can combine existing MATLAB functions and Simulink blocks with Altera
DSP Builder blocks and Altera intellectual property (IP) MegaCore functions to link
system-level design and implementation with DSP algorithm development. In this
way, DSP Builder allows system, algorithm, and hardware designers to share a
common development platform.
The DSP Builder Signal Compiler block reads Simulink Model Files (. mdl ) that
contain other DSP Builder blocks and MegaCore functions. Signal Compiler then
generates the VHDL files and Tcl scripts for synthesis, hardware implementation, and
simulation.
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
November 2013 Altera Corporation
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